Çavuşlu, Mehmet AliKarakaya, Fuat2024-11-072024-11-072010978-142449671-6https://doi.org/10.1109/SIU.2010.5653126https://hdl.handle.net/11480/1096118th IEEE Signal Processing and Communications Applications Conference, SIU 2010 -- 22 April 2010 through 24 April 2010 -- Diyarbakir -- 83388In this paper, hardware implementation of the Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) based on FPGA is explained. DWT and IDWT algorithms are implemented on the Altera Cyclone-II FPGA. Filtering processes of rows and columns are seriatim applied as in level-by-level architecture. But both addressing for read/write and DWT/IDWT processes are implemented via only one filter by checking kind of filter to be applied. This usage has got advantages of both elapsed times for read/write processes and cost of hardware area. Implementation DWT and IDWT on the hardware is required only 2% hardware area with this approximation. ©2010 IEEE.trinfo:eu-repo/semantics/closedAccessDiscrete wavelet transformsSignal processingAltera cyclonesFiltering processHardware implementationsInverse discrete wavelet transformsHardwareConference Object14114410.1109/SIU.2010.56531262-s2.0-78651442166N/A