Çavuşlu M.A.Karakaya F.Balkoca A.2019-08-012019-08-0120169.78151E+12https://dx.doi.org/10.1109/SIU.2016.7495709https://hdl.handle.net/11480/183724th Signal Processing and Communication Application Conference, SIU 2016 -- 16 May 2016 through 19 May 2016 -- -- 122605Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study. © 2016 IEEE.trinfo:eu-repo/semantics/closedAccessDe-interlacerFPGAConference Object18919210.1109/SIU.2016.74957092-s2.0-84982786708N/A