Yazar "Karakaya F." seçeneğine göre listele

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  • Küçük Resim Yok
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    FPGA implementation of extended Kalman filter for speed-sensorless control of induction motors
    (Institution of Engineering and Technology, 2014) Inan R.; Barut M.; Karakaya F.
    This paper presents a hardware in the loop (HIL) system including the implementation of an Extended Kalman Filter (EKF) based estimator on the Field Programmable Gate Array (FPGA) for speed-sensorless control of IM. The implemented EKF algorithm simultaneously estimates stator currents (i sa and isß), stator fluxes (?s? and ?sß), rotor angular velocity (?m), and load torque (tL) by assuming that stator voltages and currents are available. The HIL system also includes stator currents and fluxes based IM model which provides actual stator currents to the EKF algorithm and is also utilized to validate the flux, speed and load torque estimations of the implemented EKF algorithm. Virtex-5 VSX110T FPGA evolution board is used for this real-time application. The FPGA board is programmed via Very High Speed Integrated Circuit Hardware Description Language (VHDL) in order to develop both IM model and the EKF algorithm. ISE Design Suit Interface is used as debugger and compiler. The results obtained from the EKF and IM model developed on FPGA are graphically compared to verify the sufficiency of estimation performance of the EKF algorithm and demonstrate that EKF algorithm is implemented successfully with less computational time (less sampling time for each recursive operation) due to the inherent parallel signal processing ability of FPGA.
  • Küçük Resim Yok
    Öğe
    FPGA implementation of extended Kalman Filter for speedsensorless control of induction motors
    (Institution of Engineering and Technology, 2014) Inan R.; Barut M.; Karakaya F.
    This paper presents a hardware in the loop (HIL) system including the implementation of an Extended Kalman Filter (EKF) based estimator on the Field Programmable Gate Array (FPGA) for speed-sensorless control of IM. The implemented EKF algorithm simultaneously estimates stator currents (is? and isß), stator fluxes (?s? and ?sß), rotor angular velocity (?m), and load torque (tL) by assuming that stator voltages and currents are available. The HIL system also includes stator currents and fluxes based IM model which provides actual stator currents to the EKF algorithm and is also utilized to validate the flux, speed and load torque estimations of the implemented EKF algorithm. Virtex-5 VSX110T FPGA evolution board is used for this real-time application. The FPGA board is programmed via Very High Speed Integrated Circuit Hardware Description Language (VHDL) in order to develop both IM model and the EKF algorithm. ISE Design Suit Interface is used as debugger and compiler. The results obtained from the EKF and IM model developed on FPGA are graphically compared to verify the sufficiency of estimation performance of the EKF algorithm and demonstrate that EKF algorithm is implemented successfully with less computational time (less sampling time for each recursive operation) due to the inherent parallel signal processing ability of FPGA.
  • Küçük Resim Yok
    Öğe
    Hardware emulation of HOG and AMDF based scale and rotation invariant robust shape detection
    (2012) Peker M.; Altun H.; Karakaya F.
    In this study, a hardware emulation of HOG and AMDF based scale and rotation invariant robust shape detection for Field Programmable Gate Arrays (FPGA) is described. For this purpose, a robust algorithm with light-computational load has been developed based on features extracted from histogram of oriented gradients (HOG). A normalization scheme is proposed to obtain scale-invariant robust features using HOG algorithm. Also a novel method for shape detection is proposed using Average Magnitude Difference Function (AMDF) which leads to a rotation-invariant and computationally light shape detection method. It is shown that the proposed method is robust against noise as well. Also it is indicated that the performance of the method is highly satisfactory for implementation on real-life industrial problems. © 2012 IEEE.
  • Küçük Resim Yok
    Öğe
    Implementation of edge dependent interpolation based de-interlacer on FPGA [Kenar Bagimli Ara Degerleme Yöntemi Kullanarak De-Interlacer Işleminin FPGA Tabanli Gerçeklenmesi]
    (Institute of Electrical and Electronics Engineers Inc., 2016) Çavuşlu M.A.; Karakaya F.; Balkoca A.
    Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study. © 2016 IEEE.