Yazar "Uzam, Murat" seçeneğine göre listele

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    A New Approach for the Ladder Logic Implementation of Ramadge-Wonham Supervisors
    (IEEE, 2009) Uzam, Murat; Gelen, Gokhan; Dalci, Recep; Salihbegovic, A; Supic, H; Velagic, J; Sadzak, A
    In this paper, a new approach is proposed for the ladder logic code implementation of Ramadge-Wonham (RW) supervisors. The proposed method deals mainly with the assignment of actions (output signals) to the related states of RW supervisors. To-date there is no general method to solve this problem. In this paper, this task is accomplished by means of a very effective and easy to use technique. Once a RW supervisor assigned with actions is obtained, the conversion of this supervisor into ladder logic code is straight forward for PLC implementation. The effectiveness of the proposed method is demonstrated by means of a manufacturing system consisting of two machines and one buffer.
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    A new approach for the ladder logic implementation of Ramadge-Wonham supervisors
    (2009) Uzam, Murat; Gelen, Gökhan; Dalci, Recep
    In this paper, a new approach is proposed for the ladder logic code implementation of Ramadge-Wonham (RW) supervisors. The proposed method deals mainly with the assignment of actions (output signals) to the related states of RW supervisors. To-date there is no general method to solve this problem. In this paper, this task is accomplished by means of a very effective and easy to use technique. Once a RW supervisor assigned with actions is obtained, the conversion of this supervisor into ladder logic code is straight forward for PLC implementation. The effectiveness of the proposed method is demonstrated by means of a manufacturing system consisting of two machines and one buffer. ©2009 IEEE.
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    An iterative synthesis approach to Petri net-based deadlock prevention policy for flexible manufacturing systems
    (IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2007) Uzam, Murat; Zhou, MengChu
    This paper proposes an iterative synthesis approach to Petri net (PN)-based deadlock prevention policy for flexible manufacturing systems (FMS). Given the PN model (PNM) of an FMS prone to deadlock, the goal is to synthesize a live controlled PNM. Its use for FMS control guarantees its deadlock-free operation and high performance in terms of resource utilization and system throughput. The proposed method is an iterative approach. At each iteration, a first-met bad marking is singled out from the reachability graph of a given PNM. The objective is to prevent this marking from being reached via a place in variant of the PN. A well-established invariant-based control method is used to derive a control place. This process is carried out until the net model becomes live. The proposed method is generally applicable, easy to use, effective, and straightforward although its off-line computation is of exponential complexity. Two FMS are used to show its effectiveness and applicability.
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    Asynchronous implementation of discrete event controllers based on safe automation Petri nets
    (SPRINGER LONDON LTD, 2009) Uzam, Murat; Koc, I. Burak; Gelen, Goekhan; Aksebzeci, B. Hakan
    In this paper, a new method is proposed for digital hardware implementation of Petri net-based specifications. The purpose of this paper is to introduce a new discrete event control system paradigm, where the control system is modeled with extended Petri nets and implemented as an asynchronous controller using circuit elements. The applicability of the proposed method is demonstrated by an asynchronous implementation of a Petri net-based discrete event control system (DECS) for an experimental manufacturing system using a Xilinx field programmable gate array (FPGA). Unlike microprocessor, microcontroller or programmable logic controller (PLC)-based software implementations or hardware-based synchronous implementations, the implementation method used in this paper is asynchronous and based on hardware offering very high speed to control fast plants at low cost. This paper is expected to serve as a guideline to show how to obtain very high speed, concurrent and asynchronous Petri net-based controllers.
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    Deadlock control of concurrent manufacturing processes sharing finite resources
    (SPRINGER LONDON LTD, 2008) Li, ZhiWu; Uzam, Murat; Zhou, MengChu
    A novel deadlock control policy is developed for modeling the concurrent execution of manufacturing processes with limited shared resources through a class of nets, (ESPR)-P-3. A relevant property of the system behavior is that it is deadlock-free. Recent work has shown that deadlock situations in a plant system can be easily characterized by the structural analysis of the system, particularly, in terms of unmarked or insufficiently marked siphons in its Petri net model. The strict minimal siphons in a plant (ESPR)-P-3 net model are divided into elementary and dependent ones. The proposed deadlock prevention policy is to make all siphons satisfy maximal cs-property when the elementary siphons in the plant Petri net model are properly supervised via explicitly adding monitors for them with appropriate initial markings. Compared with the existing approaches in the literature, the advantage of the policy is that a much smaller number of supervisory places (monitors) are added and unnecessary iterative processes are avoided. Finally, its application is illustrated by a flexible manufacturing example.
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    General purpose, cheap and flexible contact debouncer
    (NEXUS MEDIA COMMUNICATIONS LTD, 2006) Uzam, Murat
    [Abstract Not Available]
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    Identification and elimination of redundant control places in petri net based liveness enforcing supervisors of FMS
    (SPRINGER LONDON LTD, 2007) Uzam, Murat; Li, Zhiwu; Zhou, MengChu
    In the past two decades, a number of Petri-net-based approaches were proposed for deadlock prevention in flexible manufacturing systems (FMS). An FMS is modeled as a Petri net, and then the controller or the liveness enforcing supervisor (LES) is computed as a Petri net. A live Petri net (LPN) guarantees deadlock-free operations of the modeled FMS. An LES consists of a number of control places (CPs) and their related arcs. To-date most of the attention has been paid to make the underlying Petri net models live without questioning whether or not all of the computed CPs are necessary. It is often the case that the number of CPs determined by these approaches is not minimal. Reducing it in order to reduce the complexity of the controlled system is an important issue that was not tackled before. To address this problem, this paper proposes a redundancy test for an LES of an FMS. The proposed approach takes an LPN model, controlled by n CPs, as input and in the existence of any redundant CPs it produces redundant and necessary CPs. The proposed approach is applicable to any LPN consisting of a Petri net model (PNM), controlled by means of a set of CPs.
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    Novel analysis of Petri-net-based controllers by means of TCT implementation tool of supervisory control theory
    (MAEJO UNIV, 2010) Gelen, Gokhan; Uzam, Murat
    The control of discrete event systems (DES) has been widely studied in the past two decades. Finite-state automata (FSA) and Petri nets (PN) are the two principal modelling formalisms for this study. Supervisory control theory (SCT), based on language and FSA concepts, is a well established framework for the study of discrete event control systems (DECS). PN-based approaches to the control design have been considered as an alternative framework. In the PN-based control of DES, given an uncontrolled PN model of a system and a set of specifications, a PN-based controller consisting of monitors (control places) is synthesised to solve the problem. In general, forbidden-state specifications are considered. Another heavily studied specification is to obtain the live system behaviour (non-blockingness in SCT terminology) for a given PN model by computing a PN-based controller. Unfortunately, PN-based analysis tools cannot deal with uncontrollable transitions. Therefore, to date there is no general technique for the correctness analysis of the computed PN-based controllers. This paper proposes a novel and general methodology to carry out the correctness analysis for the computed PN-based controllers by using the TCT implementation tool of SCT. Three examples are considered for illustration.
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    On suboptimal supervisory control of Petri nets in the presence of uncontrollable transitions via monitor places
    (SPRINGER LONDON LTD, 2010) Uzam, Murat
    Recently, a study has been presented for suboptimal supervisory control of Petri nets via monitor (control) places in the presence of uncontrollable transitions. To enforce a generalized mutual exclusion constraint (GMEC) suboptimally on a plant Petri net with uncontrollable transitions, a set of monitor places has been provided to choose from. There are two main results of this study, the first of which is that "there is not an optimal solution to the problem of computing a monitor-based controller to enforce a GMEC on a plant net in the presence of uncontrollable transitions". The second result deals with the computation of monitor places for the suboptimal supervisory control in such Petri nets. In this paper, it is shown that there may be an optimal solution to the problem of computing a monitor-based controller to enforce a GMEC on a plant net in the presence of uncontrollable transitions. To do this, an example Petri net is considered and then two different optimal (maximally permissive) solutions are provided for this Petri net.
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    PLC wiht PIC16F648A microcontroller
    (2010) Uzam, Murat
    Murat Uzam presents solutions for the seven control scenarios for a remotely-controlled model gate system. When BO (10.0) is being pressed, the gate will open. However, in this case if 80 is released then the gate will stop. This means that the program does not remember whether or not the BO was pressed. Figure 6. In this Once B0 is pressed, with the help of NO contact Q0.0 connected in parallel to the NO contact 10.0, the gate will open. Similarly, once B1 is pressed, with the help of NO contact of Q0.1 connected in parallel to the NO contact 10.1, the gate will close. When the gate is opened completely, the motor will stop with the help of NC contact of 10.2 inserted before the output Q0.0. If the gate is not opening and if the NO contact of TON-8Q0 is closed, then the gate will close with the help of NO contact QO. 1 connected in parallel to the NO contact of TON-8Q0.
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    PLC with PIC16F64848A microcontroller
    (2010) Uzam, Murat
    The microcontroller based PLC which describes priority encoder macros is discussed. An encounter is circuit that changes a set of signals into a code. Encoders are used to reduce the number of bits needed to represent some given data either in data storage or in data transmission. A priority is assigned to each of the input lines so that when multiple requests are made, the encoder output the index value of the input line with the highest priority. There are six priority encoder macros. It can be seen that the output binary code is generated based on the highest priority input signal present in the eight input lines.
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    PLC with PIC16F648A Micrc: Controller - Part 4
    (2009) Uzam, Murat
    The study focused on a project on a microcontroller-based PLC, describing the flip-flop based macros as r-edge (rising edge detector), f-edge (falling edge detector), latch0, latch and so on. The edge detection mechanism is required to define each macro, using 8-bit variables such as RED-Rising Edge Detector, DFF-RED-Rising Edge Detector for D flip-flop, DIFF-FED-Falling Edge Detector for T flip-flop, which are detected within the RAM data memory. The macro 'r-edge' defines eight rising edge detector functions selected with the num=0, 1.7, having a Boolean input variable, as IN passed into the macro 'W' and a Boolean output variable namely OUT, passed out through 'W'. The flip-flop based macros are proved in the study through four examples, including UZAM-plc-8i8o-ex.asm, N=7,8,9,10 to show the usage of flip=flop based macros. The other programs include 'UZAM-plc-8i8o-ex8.asm', 'UZAM-plc-8i8o-ex9.asm, and UZAM-plc-8i8o-ex10.asm.
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    PLC with PIC16F648A Micro Controller - Part 5
    (2009) Uzam, Murat
    Timers are an important electronic device, which can be used in a wide range of applications where a time delay function is required based on an input signal. All the 8-bit variables defined for timers must be cleared at the beginning of the PLC operation. The on-delay timer can be used to delay settings an output true (ON - 1) for a fixed period of time after an input signal becomes true (ON -1). The timing function is started as the input signal IN goes true, and, therefore, the elapsed time starts to increase. The ON-delay timer (TON-8) defines 8 on-delay timers selected with numbers ranging from 0-7. The on-delay timer outputs are represented by the status bits TON8-Q.num. The off-delay timer can be used to delay setting an output false (OFF-0) for a fixed period of time after an input signal goes false. The time constant 'tcnst' is an integer constant and is used to define preset time PT, which is obtained by the formula: PT = tcnst × CLK, where CLK should be used as the period of the free-running timing signals.
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    PLC with PIC16F648A Micro controller - Part 8
    (2009) Uzam, Murat
    Some of the significant aspects and functions of a macro 8-bit up/down counter (CTUD) PLC-based microcontroller are discussed. The CTUD has two inputs, such as CU and CD, while it can be used to count up one input and count down on the other. The up/down counter counts down the number of 'rising edges' detected at the input CD, while PV defines the maximum value for the counter. It is observed that the counter output Q is set true and the counting up stops when the counter reaches the PV value. The reset input R can be used to set the output Q false and clear the count value CV to zero. A Boolean variable is used as a rising edge detector to identify the rising edges of the inputs CU or CD. Another Boolean variable, called CTUD8-FLG, num is also used to carry out logical operations within the macro PLC-based microcontroller.
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    PLC with PIC16F648A Micro controller Part 6
    (2009) Uzam, Murat
    A project describing the circuit design of a pulse timer, embedded with programmable logic controller (PLC) with PIC16F648A microcontroller, is discussed. The pulse timer can be used to generate output pulses of a given time duration. Extended pulse timer (TEP) differs from the pulse timer in one point that with every state-change of the input signal from 0 to 1, the elapsed time is restarted from the beginning, thus, extending the pulse duration with another PT (preset time). The macro 'TEP-8' defines 8 extended pulse timers selected with the num = 0. The time constant 'tcnst' is an integer constant and is used to define preset time PT, which is obtained by multiplying tcnst by CLK, where CLK should be used as the period of the free-running timing signal ticks. The operation will carry on as long as the input signal IN remains true, generating the pulse trains based on PT0 and PT1. The oscillator timer (TOS) can also be used to generate pulse trains with given durations for true and false times.
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    PLC with PIC16F648A microcontroller
    (2010) Uzam, Murat
    Microcontroller based PLC with the use of demultiplex macros is discussed. Four examples have been considered namely, UZAM-plc-8i8o-exN.asm, N= 26, 27, 28, 29, to show usage of the demultiplex macros. The PIC programmer software can take the compiled file UZAM-plc-8i8o-exN.hex with PIC programmer hardware sends it to the program memory of the PIC16F648A microcontroller within the UZAM-PLC. To check the accuracy of the program, one can refer to the related information for each demultiplexer macro.
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    PLC WITH PIC16F648A MICROCONTROLLER (PART 1)
    (NEXUS MEDIA COMMUNICATIONS LTD, 2008) Uzam, Murat
    [Abstract Not Available]
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    PLC with PIC16F648A microcontroller (part 1)
    (2008) Uzam, Murat
    Some of the critical consideration for the hardware design of UZAM-PLC with PIC16F648A based on PLCs, are described. Programmable logic controllers (PLCs) are used to make different devices of different function and program memory with different number of inputs/outputs. The hardware of UZAM_PLC with PIC16F648A has a main board and I/O extension board. The main board is made of power, programming, a central processing unit (CPU), input, and outputs. A PIC programmer hardware and software with ICSP (in circuit serial programming) is used for creating programming of PIC16F648A. The input voltage for power section is 12V AC and output voltage is 12V DC and 5V DC that can be used for operating ICs and inputs. The PIC 16F648A is used to provide 4096 words of flash program memory, 256 bytes of RAM data memory, and 256 bytes of EEPROM data memory.
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    PLC with PIC16F648A Microcontroller - Part 10
    (ST JOHN PATRICK PUBL, 2009) Uzam, Murat
    [Abstract Not Available]