A fully customizable hardware implementation for general purpose genetic algorithms

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dc.contributor.authorPeker M.
dc.date.accessioned2019-08-01T13:38:39Z
dc.date.available2019-08-01T13:38:39Z
dc.date.issued2018
dc.departmentNiğde ÖHÜ
dc.description.abstractIn this work, a fully customizable general purpose genetic algorithm (GA) IP core has been proposed for field programmable gate arrays (FPGAs) using the pipeline and parallel architectures to speed up the GA process. The proposed system is implemented on FPGA and coded with very high speed integrated circuits (VHSIC) hardware description language (VHDL). The GA operators and the fitness functions are designed in a modular structure to enable the use of these modules asynchronously. The VHDL code is written with generic parameters to allow the customization of almost every parameter of the proposed FPGA IP Core depending on the problem. The proposed architecture synthesized and tested on Altera DE2-115 board with approximately 12% logic elements utilization. Results are obtained from standard optimization benchmark functions and the traveling salesman problem (TSP). In the hardware experiments, the proposed FPGA IP Core has been found the global optimum solutions for all of the standard benchmark functions and TSP. The clock cycle per generation value of the proposed FPGA IP Core has been decreased up to approximately 95% when compared with the existing implementations. For the TSP case, the proposed FPGA IP Core has reduced the run-time of the compared work approximately 75% and with optimized parameters, the reducement reached approximately 99%. For all test cases, it is concluded that the proposed core enhanced both the clock cycles needed to iterate one generation and the convergence speed of the existing GA implementations. © 2017 Elsevier B.V.
dc.identifier.doi10.1016/j.asoc.2017.09.044
dc.identifier.endpage1076
dc.identifier.issn1568-4946
dc.identifier.scopus2-s2.0-85031810970
dc.identifier.scopusqualityQ1
dc.identifier.startpage1066
dc.identifier.urihttps://dx.doi.org/10.1016/j.asoc.2017.09.044
dc.identifier.urihttps://hdl.handle.net/11480/1709
dc.identifier.volume62
dc.identifier.wosWOS:000418333500070
dc.identifier.wosqualityQ1
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.institutionauthorPeker M.
dc.language.isoen
dc.publisherElsevier Ltd
dc.relation.ispartofApplied Soft Computing Journal
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.subjectField programmable gate arrays
dc.subjectGenetic algorithms
dc.subjectHardware design languages
dc.titleA fully customizable hardware implementation for general purpose genetic algorithms
dc.typeArticle

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