Design Optimization for High-Performance Computing Using FPGA
| dc.contributor.author | Isik, Murat | |
| dc.contributor.author | Inadagbo, Kayode | |
| dc.contributor.author | Aktas, Hakan | |
| dc.date.accessioned | 2024-11-07T13:23:53Z | |
| dc.date.available | 2024-11-07T13:23:53Z | |
| dc.date.issued | 2024 | |
| dc.department | Niğde Ömer Halisdemir Üniversitesi | |
| dc.description | 10th Annual International Conference on Information Management and Big Data (SIMBig) -- DEC 13-15, 2023 -- Inst Politecnico Nacl, Centro Investigac Computac, Mexico City, MEXICO | |
| dc.description.abstract | Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations in several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs have not been widely used for high-performance computing, primarily because of their programming complexity and difficulties in optimizing performance. We optimize Tensil AI's open-source inference accelerator for maximum performance using ResNet20 trained on CIFAR in this paper in order to gain insight into the use of FPGAs for high-performance computing. In this paper, we show how improving hardware design, using Xilinx Ultra RAM, and using advanced compiler strategies can lead to improved inference performance. We also demonstrate that running the CIFAR test data set shows very little accuracy drop when rounding down from the original 32bit floating point. The heterogeneous computing model in our platform allows us to achieve a frame rate of 293.58 frames per second (FPS) and a %90 accuracy on a ResNet20 trained using CIFAR. The experimental results show that the proposed accelerator achieves a throughput of 21.12 Giga-Operations Per Second (GOP/s) with a 5.21W on-chip power consumption at 100 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency. | |
| dc.description.sponsorship | Soc Mexicana Inteligencia Artificial,N Amer Chapter Assoc Computat Linguist | |
| dc.identifier.doi | 10.1007/978-3-031-63616-5_11 | |
| dc.identifier.endpage | 156 | |
| dc.identifier.isbn | 978-3-031-63615-8 | |
| dc.identifier.isbn | 978-3-031-63616-5 | |
| dc.identifier.issn | 1865-0929 | |
| dc.identifier.issn | 1865-0937 | |
| dc.identifier.scopus | 2-s2.0-85199669245 | |
| dc.identifier.scopusquality | Q4 | |
| dc.identifier.startpage | 142 | |
| dc.identifier.uri | https://doi.org/10.1007/978-3-031-63616-5_11 | |
| dc.identifier.uri | https://hdl.handle.net/11480/13758 | |
| dc.identifier.volume | 2142 | |
| dc.identifier.wos | WOS:001295286100011 | |
| dc.identifier.wosquality | N/A | |
| dc.indekslendigikaynak | Web of Science | |
| dc.indekslendigikaynak | Scopus | |
| dc.language.iso | en | |
| dc.publisher | Springer International Publishing Ag | |
| dc.relation.ispartof | Information Management and Big Data, Simbig 2023 | |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | |
| dc.rights | info:eu-repo/semantics/closedAccess | |
| dc.snmz | KA_20241106 | |
| dc.subject | High-performance computing | |
| dc.subject | Tensil AI | |
| dc.subject | Design optimization | |
| dc.subject | FPGA | |
| dc.subject | Open-source inference accelerator | |
| dc.title | Design Optimization for High-Performance Computing Using FPGA | |
| dc.type | Conference Object |
