Implementation of Edge Dependent Interpolation Based De-Interlacer on FPGA
Küçük Resim Yok
Tarih
2016
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
IEEE
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study.
Açıklama
24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEY
Anahtar Kelimeler
FPGA, De-interlacer
Kaynak
2016 24TH SIGNAL PROCESSING AND COMMUNICATION APPLICATION CONFERENCE (SIU)
WoS Q Değeri
N/A
