Implementation of Edge Dependent Interpolation Based De-Interlacer on FPGA

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dc.contributor.authorCavuslu, Mehmet Ali
dc.contributor.authorKarakaya, Fuat
dc.contributor.authorBalkoca, Alisan
dc.date.accessioned2019-08-01T13:38:39Z
dc.date.available2019-08-01T13:38:39Z
dc.date.issued2016
dc.departmentNiğde ÖHÜ
dc.description24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEY
dc.description.abstractInterlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study.
dc.description.sponsorshipIEEE, Bulent Ecevit Univ, Dept Elect & Elect Engn, Bulent Ecevit Univ, Dept Biomed Engn, Bulent Ecevit Univ, Dept Comp Engn
dc.identifier.endpage192
dc.identifier.isbn978-1-5090-1679-2
dc.identifier.startpage189
dc.identifier.urihttps://hdl.handle.net/11480/3748
dc.identifier.wosWOS:000391250900025
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Science
dc.institutionauthor[0-Belirlenecek]
dc.language.isotr
dc.publisherIEEE
dc.relation.ispartof2016 24TH SIGNAL PROCESSING AND COMMUNICATION APPLICATION CONFERENCE (SIU)
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.subjectFPGA
dc.subjectDe-interlacer
dc.titleImplementation of Edge Dependent Interpolation Based De-Interlacer on FPGA
dc.typeConference Object

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