Yazar "Cavuslu, Mehmet Ali" seçeneğine göre listele

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    Comparison of Number Formats on FPGA-Based OFDM Modem Architecture
    (IEEE, 2013) Sahin, Suhap; Kavak, Adnan; Cavuslu, Mehmet Ali
    It is preferable for wireless operators to use the existing infrastructure as possible for different services such as GSM, 3G and Wimax. This becomes possible with the development of software defined base stations. But, to obtain desired performance and flexibility in signal processing at software defined base stations needs to be implemented instead of traditional processors and ASIC modem on programmable processors. The purpose of this thesis is implementing of the OFDM modem architecture on FPGA by using IEEE-754 floating point and IQ-Math fixed point number format. Two different OFDM modem design implemented by using IEEE-754 and IQ-Math, compared with basis of the usage of FPGA hardware resources, design clock frequency and the sensitivity of number formats criteria.
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    FPGA implementation of neuro-fuzzy system with improved PSO learning
    (PERGAMON-ELSEVIER SCIENCE LTD, 2016) Karakuzu, Cihan; Karakaya, Fuat; Cavuslu, Mehmet Ali
    This paper presents the first hardware implementation of neuro-fuzzy system (NFS) with its metaheuristic learning ability on field programmable gate array (FPGA). Metaheuristic learning of NFS for all of its parameters is accomplished by using the improved particle swarm optimization (iPSO). As a second novelty, a new functional approach, which does not require any memory and multiplier usage, is proposed for the Gaussian membership functions of NFS. NFS and its learning using iPSO are implemented on Xilinx Virtex5 xc5vlx110-3ff1153 and efficiency of the proposed implementation tested on two dynamic system identification problems and licence plate detection problem as a practical application. Results indicate that proposed NFS implementation and membership function approximation is as effective as the other approaches available in the literature but requires less hardware resources. (C) 2016 Elsevier Ltd. All rights reserved.
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    FPGA-Based Implementation of Basic Image Processing Applications as Low-Cost IP Core
    (IEEE, 2018) Altuncu, Mehmet Ali; Kosten, Mehmet Muzaffer; Cavuslu, Mehmet Ali; Sahin, Suhap
    With technology, rapidly developing image sensors have begun to be used in many areas, from smart phones to unmanned vehicles. In particular, systems that have to process many images at the same time, such as unmanned vehicles, require a high amount of processing power and use expensive equipment. In this work, we describe FPGA based implementation of basic image processing applications that can work on low cost FPGA families for use in applications with high processing power. With the IP core, users can easily perform mirroring, inversion, negation, thresholding, brightness and contrast enhancement / reduction on the image. The IP core platform is designed to be independently. Synthesis results are given with reference to Xilinx's Spartan 7 FPGA. The results show that the developed IP core has a low hardware cost.
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    Implementation of Edge Dependent Interpolation Based De-Interlacer on FPGA
    (IEEE, 2016) Cavuslu, Mehmet Ali; Karakaya, Fuat; Balkoca, Alisan
    Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study.
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    Implementation of HOG algorithm for Real Time Object Recognition Applications on FPGA based Embedded System
    (IEEE, 2009) Karakaya, Fuat; Altun, Halis; Cavuslu, Mehmet Ali
    Recent years HOG algorithm has been used to recognize objects in images, with complex content, with a very high success rate. Hardware implementation of this algorithm is very important because of the fact that it can be used in many object recognition applications. In this work HOG algorithm is implemented on FPGA to recognize different geometrical figures with a very high success rate. Objects vertical and horizontal edges have been sharpened using edge detection algorithms to calculate magnitude and angle of the local gradients. Obtained result are used to construct the histograms of gradient orientation. It is observed that each constructed histogram have distinctive features for every object. Rule based classifiers has been used to implement a successful real time object recognition approach on embedded system.
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    Neural identification of dynamic systems on FPGA with improved PSO learning
    (ELSEVIER SCIENCE BV, 2012) Cavuslu, Mehmet Ali; Karakuzu, Cihan; Karakaya, Fuat
    This work introduces hardware implementation of artificial neural networks (ANNs) with learning ability on field programmable gate array (FPGA) for dynamic system identification. The learning phase is accomplished by using the improved particle swarm optimization (PSO). The improved PSO is obtained by modifying the velocity update function. Adding an extra term to the velocity update function reduced the possibility of stucking in a local minimum. The results indicates that ANN, trained using improved PSO algorithm, converges faster and produces more accurate results with a little extra hardware utilization cost. (C) 2012 Elsevier B.V. All rights reserved.